# zr_scanout mutants: NAME<TAB>class<TAB>sed on zr_scanout.sv. req = must FAIL tb_zr_ssys (4 frames, one window,
# latency 20, 30 % waitrequest, 50 % background load). Each misreads one gospel fact:
#   S1 expanded-address row stride 256 instead of 512 (midzeus_v.cpp:135)
#   S2 display line stride 128 words instead of 256 (READPIX y << 10 16-bit words, :102)
#   S3 odd pixel in the low half (READPIX x & 1 selects the half)
#   S4 first visible column 126 instead of 127 (C6 low half / visible min_x)
#   S5 display reads the other line-buffer bank (line parity)
#   S6 the fetch writes the bank being DISPLAYED (vnext) instead of the fetched line's
#   S7 vtotal 277 instead of 278 (set_raw / CA high half)
S1	req	s/{disp_cc\[24:16\], 9'd0}/{disp_cc[24:16], 8'd0}/
S2	req	s/{4'd0, want\[7:0\], 8'd0}/{5'd0, want[7:0], 7'd0}/
S3	req	s/(xa\[0\] ? lb_rd\[30:16\] : lb_rd\[14:0\])/(xa[0] ? lb_rd[14:0] : lb_rd[30:16])/
S4	req	s/assign xa = hc - 10'(HBEGIN);/assign xa = hc - 10'(HBEGIN - 1);/
S5	req	s/assign lb_ra = {vc\[0\], xa\[8:1\]};/assign lb_ra = {~vc[0], xa[8:1]};/
S6	req	s/ftgt <= want; f_bank <= want\[0\];/ftgt <= want; f_bank <= vnext[0];/
S7	req	s/parameter int VTOTAL = 278/parameter int VTOTAL = 277/
