# zr_setup8 mutants: NAME<TAB>class<TAB>kind<TAB>sed. class req = must FAIL the streaming tap gate (range + x span on
# every extent, params + exc on every used one, plus the sim-only hazard flag: slot ownership + A-instance unit
# collisions). kind T = mutate zr_setup8.sv, U = mutate fp32_units.sv.
# ---- v5's set, re-targeted at v8 text (meanings in mutate_zr_setup5.sh) ----
V1	req	T	s/p_fully <= {r.v\[31\], r.v\[30:23\] - 8'd1, r.v\[22:0\]};/p_fully <= r.v;/
V2	req	T	s/begin ap_a = a_rp\[p\]; ap_b = hb_lp\[a_slot\[i\]\]\[p\]; ap_sub = 1'b1; end/begin ap_a = hb_lp[a_slot[i]][p]; ap_b = a_rp[p]; ap_sub = 1'b1; end/
V3	req	T	s/mp_a = (p == 0) ? as_y : ldy;/mp_a = ldy;/
V4	req	T	s/P_ADVL: if (fp_gt(p_fully, ps_y2\[p_ps\]\[p_ls\]\[p_li\])/P_ADVL: if (!fp_lt(p_fully, ps_y2[p_ps][p_ls][p_li])/
V5	req	T	s/begin ea_a = pp2\[p\]; ea_b = q_p1\[pre_s\]\[p\]; end/begin ea_a = q_p1[pre_s][p]; ea_b = pp2[p]; end/
V6	req	T	s/if (a < ps_cminx\[a_ps\[i\]\]) a = ps_cminx\[a_ps\[i\]\];/;/
V7	req	T	s/if (fp_lt(v\[mk\]\[1\], v\[minv\]\[1\])) minv <= mk;/if (!fp_gt(v[mk][1], v[minv][1])) minv <= mk;/
V8	req	T	s/^  assign fe_rc_ok = .*;/  assign fe_rc_ok = 1'b1;/
V9	req	T	s/if (last) begin p_ps <= ~p_ps; pst <= P_WAIT; ps_issued\[p_ps\] <= 1'b1; end/if (last) begin p_ps <= ~p_ps; pst <= P_WAIT; ps_issued[p_ps] <= 1'b1; ps_valid[p_ps] <= 1'b0; end/
V10	req	T	s/k = ca\[i\] + 8'd1;/k = ca[i];/
V11	req	T	s/sl = (reserved == 2'd0) ? hb_head : ~hb_head;/sl = hb_head;/
U1	req	U	s/stk = q\[0\] | (rem != 25'd0);/stk = q[0];/
# ---- v6: empty-extent fast path ----
E1	req	T	s/if (q == 8'(4\*L + 1) \&\& !a_empty\[i\]) begin rcp_start/if (q == 8'(4*L + 1)) begin rcp_start/
# ---- v7: pipelined edge jobs ----
#   J1 a reciprocal answers into slot 0 always   J2 POST writes x1 of the PRE slot   J3 PRE starts on a busy reciprocal
#   J4 PRE reuses a slot POST still holds
J1	req	T	s/erc_s\[pre_u\] <= pre_s;/erc_s[pre_u] <= 2'd0;/
J2	req	T	s/rx_wd = q_x1\[qs\];/rx_wd = q_x1[pre_s];/
J3	req	T	s/ \&\& !erc_busy\[pj\[0\]\] \&\& !erc_done\[pj\[0\]\]//
J4	req	T	s/if (pj != nj \&\& !q_busy\[pre_s\] \&\&/if (pj != nj \&\&/
# ---- v8: two overlapped A instances ----
#   G1 any start gap >= 16 allowed (adder collisions at 17 18 21 22)   G2 prep re-enters a fully issued slot
#   G3 a third start while both instances run                          G4 the new instance is always instance 0
G1	req	T	s/return !busy || c == 8'd15 || c == 8'd18 || c == 8'd19 || c >= 8'd22;/return !busy || c >= 8'd15;/
G2	req	T	s/P_WAIT: if (ps_valid\[p_ps\] \&\& !ps_issued\[p_ps\]) begin/P_WAIT: if (ps_valid[p_ps]) begin/
G3	req	T	s/assign astart = !(a_busy\[0\] \&\& a_busy\[1\]) \&\& /assign astart = /
G4	req	T	s/assign a_new = a_busy\[0\];/assign a_new = 1'b0;/
