# zr_memsys mutants: NAME<TAB>class<TAB>sed on zr_memsys.sv. req = must FAIL at least one of: the zr_memsys unit gate
# (tb_zr_memsys, 400k clocks, latency 20, 60 % waitrequest) or the zr_rsys gate (renderer + memsys + DDR model) on
# attract + the reference window (latency 30, 30 % waitrequest).
#   H1 read hazard ignores the open run          H2 read hazard ignores queued colour writes
#   H3 read hazard ignores queued descriptors    H4 front-end wave-RAM-1 access ignores the coalescer
#   C1 merge replaces the byte mask              C2 merge takes the wrong half of the word
#   C3 a closed run loses its last beat          C4 a pixel pair lands in the wrong half of the 64-bit word
#   C5 no idle flush (an open run is never written)
#   R1 colour read returns lane 0 always         R2 texture responses routed as front-end responses
#   R3 a front-end write pops the colour beat FIFO
#   A1 a front-end write does not wait for OLDER reads      A2 a YOUNGER colour write may overtake a front-end access
#   A3 a texture read ignores an older front-end write      A4 ages ignore the other queue's pops
#   A5 the front-end hazard counts YOUNGER colour writes (v3 ordering inversion)
#   P1 contiguity broken (every word its own run) -- performance only
#   H3s scanout hazard ignores queued descriptors (sc OUTRANKS a queued run, so this check is load-bearing)
# equiv = proven equivalent, survival expected:
#   H3  a queued run outranks cr and a refused write blocks everything below it, so cr never passes a descriptor
#       (the check is redundant with arbitration; kept as defence, H3s guards the sc copy that is not)
#   C4  MK4 writes only the colour half: cw_addr[2] AND cw_addr[1] are always 0, so the swap changes nothing
H1	req	s/      if (in_run(cr_word, bu_start, bu_n + 6'd1)) hz_cr = 1'b1;/      if (1'b0) hz_cr = 1'b1;/
H2	req	s/      if (cr_word == qw_word\[k\] \&\& qwc\[k\] == 2'd0) hz_cr = 1'b1;/      if (1'b0) hz_cr = 1'b1;/
H3	equiv	s/      if (in_run(cr_word, df_q\[k\]\[34:6\], df_q\[k\]\[5:0\])) hz_cr = 1'b1;/      if (1'b0) hz_cr = 1'b1;/
H4	req	s/    ok_fm = qfm_v \&\& !hz_fm \&\&/    ok_fm = qfm_v \&\&/
C1	req	s/          ob_mask <= ob_mask | cw_m8;/          ob_mask <= cw_m8;/
C2	req	s/          for (int b = 0; b < 8; b++) if (cw_m8\[b\]) ob_data\[8\*b +: 8\] <= cw_d64\[8\*b +: 8\];/          for (int b = 0; b < 8; b++) if (cw_m8[b]) ob_data[8*(b^4) +: 8] <= cw_d64[8*b +: 8];/
C3	req	s/    df_iv = 1'b0; df_in = {bu_start, bu_n + 6'd1}; /    df_iv = 1'b0; df_in = {bu_start, bu_n}; /
C4	equiv	s/    cw_d64 = q_addr\[2\] ? {q_data, 32'd0} : {32'd0, q_data};/    cw_d64 = q_addr[1] ? {q_data, 32'd0} : {32'd0, q_data};/
C5	req	s/ || (ob_v \&\& idle_cnt >= 8'(IDLE_FLUSH));/;/
R1	req	s/assign cr_data  = g_rsp_data\[16\*g_rsp_tag\[1:0\] +: 16\];/assign cr_data  = g_rsp_data[15:0];/
R2	req	s/assign w0_rvalid = rd \&\& r_cl == C_W0;/assign w0_rvalid = rd \&\& r_cl == C_FM;/
R3	req	s/  assign bf_pop = !w_src_fm \&\& g_w_ready \&\& bf_ov;/  assign bf_pop = g_w_ready \&\& bf_ov;/
A1	req	s/ \&\& !(fm_we_q \&\& older_rd);/;/
A2	req	s/    cw_take  = qcw_v \&\& !qcw_young \&\&/    cw_take  = qcw_v \&\&/
A3	req	s/      if (2'(k) < w0_y \&\& WR0_BASE/      if (1'b0 \&\& WR0_BASE/
A4	req	s/      yn = on - 2'(opop);/      yn = on;/
A5	req	s/fm_word == qw_word\[k\] \&\& qwf\[k\] == 2'd0/fm_word == qw_word[k]/
P1	perf	s/    cw_cont  = ob_v \&\& cw_word == ob_word + 29'd1 \&\& bu_n < 6'd31;/    cw_cont  = 1'b0;/
H3s	req	s/      if (overlap(sc_w29, sc_n, df_q\[k\]\[34:6\], df_q\[k\]\[5:0\])) hz_sc = 1'b1;/      if (1'b0) hz_sc = 1'b1;/
